Field
This disclosure relates generally to semiconductor structures, and more specifically, to split gate memory cell structures.
Related Art
Split gate memory cell structures, which include both a select gate and a control gate, are typically used as bitcell storage devices within nonvolatile memory arrays. The use of a separate select gate for the bitcells in such arrays allows for improved isolation and reduced bitcell disturb during programming and reading of the bitcells. In split gate memory cells, the gap region between select gate and control gate is a weak spot for voltage breakdown. The region is subjected to repeated high erase voltage during non-volatile memory cell operation.